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Espressif Systems /ESP32-P4 /HP_SYS_CLKRST /SOC_CLK_CTRL0

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Interpret as SOC_CLK_CTRL0

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (REG_CORE0_CLIC_CLK_EN)REG_CORE0_CLIC_CLK_EN 0 (REG_CORE1_CLIC_CLK_EN)REG_CORE1_CLIC_CLK_EN 0 (REG_MISC_CPU_CLK_EN)REG_MISC_CPU_CLK_EN 0 (REG_CORE0_CPU_CLK_EN)REG_CORE0_CPU_CLK_EN 0 (REG_CORE1_CPU_CLK_EN)REG_CORE1_CPU_CLK_EN 0 (REG_TCM_CPU_CLK_EN)REG_TCM_CPU_CLK_EN 0 (REG_BUSMON_CPU_CLK_EN)REG_BUSMON_CPU_CLK_EN 0 (REG_L1CACHE_CPU_CLK_EN)REG_L1CACHE_CPU_CLK_EN 0 (REG_L1CACHE_D_CPU_CLK_EN)REG_L1CACHE_D_CPU_CLK_EN 0 (REG_L1CACHE_I0_CPU_CLK_EN)REG_L1CACHE_I0_CPU_CLK_EN 0 (REG_L1CACHE_I1_CPU_CLK_EN)REG_L1CACHE_I1_CPU_CLK_EN 0 (REG_TRACE_CPU_CLK_EN)REG_TRACE_CPU_CLK_EN 0 (REG_ICM_CPU_CLK_EN)REG_ICM_CPU_CLK_EN 0 (REG_GDMA_CPU_CLK_EN)REG_GDMA_CPU_CLK_EN 0 (REG_VPU_CPU_CLK_EN)REG_VPU_CPU_CLK_EN 0 (REG_L1CACHE_MEM_CLK_EN)REG_L1CACHE_MEM_CLK_EN 0 (REG_L1CACHE_D_MEM_CLK_EN)REG_L1CACHE_D_MEM_CLK_EN 0 (REG_L1CACHE_I0_MEM_CLK_EN)REG_L1CACHE_I0_MEM_CLK_EN 0 (REG_L1CACHE_I1_MEM_CLK_EN)REG_L1CACHE_I1_MEM_CLK_EN 0 (REG_L2CACHE_MEM_CLK_EN)REG_L2CACHE_MEM_CLK_EN 0 (REG_L2MEM_MEM_CLK_EN)REG_L2MEM_MEM_CLK_EN 0 (REG_L2MEMMON_MEM_CLK_EN)REG_L2MEMMON_MEM_CLK_EN 0 (REG_ICM_MEM_CLK_EN)REG_ICM_MEM_CLK_EN 0 (REG_MISC_SYS_CLK_EN)REG_MISC_SYS_CLK_EN 0 (REG_TRACE_SYS_CLK_EN)REG_TRACE_SYS_CLK_EN 0 (REG_L2CACHE_SYS_CLK_EN)REG_L2CACHE_SYS_CLK_EN 0 (REG_L2MEM_SYS_CLK_EN)REG_L2MEM_SYS_CLK_EN 0 (REG_L2MEMMON_SYS_CLK_EN)REG_L2MEMMON_SYS_CLK_EN 0 (REG_TCMMON_SYS_CLK_EN)REG_TCMMON_SYS_CLK_EN 0 (REG_ICM_SYS_CLK_EN)REG_ICM_SYS_CLK_EN 0 (REG_FLASH_SYS_CLK_EN)REG_FLASH_SYS_CLK_EN 0 (REG_PSRAM_SYS_CLK_EN)REG_PSRAM_SYS_CLK_EN

Description

Reserved

Fields

REG_CORE0_CLIC_CLK_EN

Reserved
REG_CORE1_CLIC_CLK_EN

Reserved
REG_MISC_CPU_CLK_EN

Reserved
REG_CORE0_CPU_CLK_EN

Reserved
REG_CORE1_CPU_CLK_EN

Reserved
REG_TCM_CPU_CLK_EN

Reserved
REG_BUSMON_CPU_CLK_EN

Reserved
REG_L1CACHE_CPU_CLK_EN

Reserved
REG_L1CACHE_D_CPU_CLK_EN

Reserved
REG_L1CACHE_I0_CPU_CLK_EN

Reserved
REG_L1CACHE_I1_CPU_CLK_EN

Reserved
REG_TRACE_CPU_CLK_EN

Reserved
REG_ICM_CPU_CLK_EN

Reserved
REG_GDMA_CPU_CLK_EN

Reserved
REG_VPU_CPU_CLK_EN

Reserved
REG_L1CACHE_MEM_CLK_EN

Reserved
REG_L1CACHE_D_MEM_CLK_EN

Reserved
REG_L1CACHE_I0_MEM_CLK_EN

Reserved
REG_L1CACHE_I1_MEM_CLK_EN

Reserved
REG_L2CACHE_MEM_CLK_EN

Reserved
REG_L2MEM_MEM_CLK_EN

Reserved
REG_L2MEMMON_MEM_CLK_EN

Reserved
REG_ICM_MEM_CLK_EN

Reserved
REG_MISC_SYS_CLK_EN

Reserved
REG_TRACE_SYS_CLK_EN

Reserved
REG_L2CACHE_SYS_CLK_EN

Reserved
REG_L2MEM_SYS_CLK_EN

Reserved
REG_L2MEMMON_SYS_CLK_EN

Reserved
REG_TCMMON_SYS_CLK_EN

Reserved
REG_ICM_SYS_CLK_EN

Reserved
REG_FLASH_SYS_CLK_EN

Reserved
REG_PSRAM_SYS_CLK_EN

Reserved

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/espressif/svd